American Institute of Mathematical Sciences

Advanced
doi: 10.3934/amc.2020078

New optimal error-correcting codes for crosstalk avoidance in on-chip data buses

Muhammad Ajmal and  Xiande Zhang ,

School of Mathematical Sciences, University of Science and Technology of China, Wu Wen-Tsun Key Laboratory of Mathematics, No. 96 Jinzhai Road, Hefei, 230026, Anhui, China

* Corresponding author: Xiande Zhang

Received  October 2019 Revised  March 2020 Published  April 2020

Fund Project: The first author is supported by the Chinese Scholarship Council at USTC, China. The second author is supported by NSFC grant 11771419, and by the Fundamental Research Funds for the Central Universities

Codes that simultaneously provide for low power dissipation, cross-talk avoidance, and error correction in the ultra deep submicron/nanometer VLSI fabrication, were recently introduced by Chee et al. in 2015. Such codes were revealed to be closely related to balanced sampling plans avoiding adjacent units, which are widely used in the statistical design of experiments. In this paper, we construct a new family of optimal codes with such properties, by determining the maximum size of packing sampling plans avoiding certain units.

Keywords: Constant weight codes, packing sampling plan avoiding adjacent units, crosstalk avoidance, packing by triples, balanced sampling plan.
Mathematics Subject Classification: Primary: 05B07, 05B40; Secondary: 94B25.
Citation: Muhammad Ajmal, Xiande Zhang. New optimal error-correcting codes for crosstalk avoidance in on-chip data buses. Advances in Mathematics of Communications, doi: 10.3934/amc.2020078
References:
[1]

D. Bertozzi, L. Benini and G. D. Micheli, Low power error resilient encoding for on-chip data buses, Proceedings of the Conference on Design, Automation and Test in Europe, IEEE Computer Society, (2002), 102–109. doi: 10.1109/DATE.2002.998256.  Google Scholar

[2]

J. A. Bondy and U. S. R. Murty, Graph Theory with Applications, American Elsevier Publishing Co., Inc., New York, 1976.  Google Scholar

[3]

D. Bryant, Y. X. Chang, C. A. Rodger and R. Wei, Two-dimensional balanced sampling plans excluding contiguous units, Communications in Statistics-Theory and Methods, 31 (2002), 1441-1455.  doi: 10.1081/STA-120006078.  Google Scholar

[4]

Y. M. Chee, C. J. Colbourn and A. C. H. Ling, Optimal memoryless encoding for low power off-chip data buses, 2006 IEEE/ACM International Conference on Computer Aided Design, IEEE, (2006), 369–374. doi: 10.1145/1233501.1233575.  Google Scholar

[5]

Y. M. Chee, C. J. Colbourn, A. C. H. Ling, H. Zhang and X. D. Zhang, Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses, Des. Codes Cryptogr., 77 (2015), 479-491.  doi: 10.1007/s10623-015-0084-4.  Google Scholar

[6]

C. J. Colbourn and A. C. H. Ling, A class of partial triple systems with applications in survey sampling, Communications in Statistics-Theory and Methods, 27 (1998), 1009-1018.  doi: 10.1080/03610929808832141.  Google Scholar

[7]

C. J. Colbourn and A. C. H. Ling, Balanced sampling plans with block size four excluding contiguous units, Australasian Journal of Combinatorics, 20 (1999), 37-46. doi: ajc.maths.uq.edu.au.  Google Scholar

[8]

C. J. Duan, A. Tirumala and S. P. Khatri, Analysis and avoidance of cross-talk in on-chip buses, HOT 9 Interconnects Symposium on High Performance Interconnects, IEEE, (2001), 133–138. doi: 10.1109/HIS.2001.946705.  Google Scholar

[9]

M. Favalli and C. Metra, Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7 (1999), 392-396.  doi: 10.1109/92.784100.  Google Scholar

[10]

A. S. Hedayat, C. R. Rao and J. Stufken, Sampling plans excluding contiguous units, Sampling, Handbook of Statist., North-Holland, Amsterdam, 6 (1988), 575-583.  doi: 10.1016/0378-3758(88)90070-5.  Google Scholar

[11]

A. Hedayat, C. Rao and J. Stufken, 24 Designs in survey sampling avoiding contiguous units, Handbook of Statistics, 6 (1988), 575-583.  doi: 10.1016/S0169-7161(88)06026-2.  Google Scholar

[12]

I. Iqbal, M. H. Tahir, M. Akhtar, S. S. A. Ghazali, J. Shabbir and N. S. Bukhari, Generalized polygonal designs with block size 3 and $\lambda = 1$, Journal of Statistical Planning and Inference, 139 (2009), 3200-3219.  doi: 10.1016/j.jspi.2009.02.018.  Google Scholar

[13]

Z. Khan, T. Arslan and A. T. Erdogan, A dual low power and crosstalk immune encoding scheme for system-on-chip buses, International Workshop on Power and Timing Modeling, Optimization and Simulation, (2004), 585–592. doi: 10.1007/978-3-540-30205-6_60.  Google Scholar

[14]

H. R. Kong, J. G. Lei and Y. Zhang, On constructions for two dimensional balanced sampling plan excluding contiguous units with block size four, Discrete Mathematics, 308 (2008), 3729-3743.  doi: 10.1016/j.disc.2007.07.065.  Google Scholar

[15]

F. J. MacWilliams and N. J. A. Sloane, The Theory of Error-Correcting Codes. I, North-Holland Mathematical Library, Vol. 16. North-Holland Publishing Co., Amsterdam-New York-Oxford, 1977.  Google Scholar

[16]

Y. Miao and L. Zhu, Existence of incomplete group divisible designs, J. Comb. Math. Comb. Comput., 6 (1989), 33-49.   Google Scholar

[17]

K. N. Patel and I. L. Markov, Error-correction and crosstalk avoidance in DSM busses, Proceedings of the 2003 International Workshop on System-level Interconnect Prediction, ACM, (2003), 9–14. doi: 10.1145/639929.639933.  Google Scholar

[18]

S. Ramprasad, N. R. Shanbhag and I. N. Hajj, A coding framework for low-power address and data busses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7 (1999), 212-221.  doi: 10.1109/92.766748.  Google Scholar

[19]

D. Rossi, V. E. S. van Dijk, R. P. Kleihorst, A. H. Nieuwland and C. Metra, Coding scheme for low energy consumption fault-tolerant bus, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW), IEEE, (2002), 8–12. doi: 10.1109/OLT.2002.1030176.  Google Scholar

[20]

J. E. Simpson, Langford sequences: Perfect and hooked, Discrete Mathematics, 44 (1983), 97-104.  doi: 10.1016/0012-365X(83)90008-0.  Google Scholar

[21]

M. R. Stan and W. P. Burleson, Bus-invert coding for low-power I/O, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3 (1995), 49-58.  doi: 10.1109/92.365453.  Google Scholar

[22]

J. Stufken, Combinatorial and statistical aspects of sampling plans to avoid the selection of adjacent units, J. Combin. Info. Syst. Sci., 18 (1993), 149-160.   Google Scholar

[23]

J. Stufken and J. H. Wright, Polygonal designs with blocks of size $k \leq 10$, Metrika, 54 (2001), 179-184.  doi: 10.1007/s001840100137.  Google Scholar

[24]

C.-L. Su, C.-Y. Tsui and A. M. Despain, Saving power in the control path of embedded processors, IEEE Design Test of Computers, 11 (1994), 24-31.  doi: 10.1109/54.329448.  Google Scholar

[25]

M. H. Tahir, I. Iqbal, M. Akhtar and J. Shabbir, Cyclic polygonal designs with block size 3 and $\lambda = 1$ for joint distance $\alpha = 6$ to $16$, Journal of Statistical Theory and Practice, 4 (2010), 203-220.  doi: 10.1080/15598608.2010.10411981.  Google Scholar

[26]

B. Victor and K. Keutzer, Bus encoding to prevent crosstalk delay, Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, (2001), 57–63. doi: 10.1109/ICCAD.2001.968598.  Google Scholar

[27]

X. M. Wang, T. Feng, J. Zhang and Y. Xu, Two-dimensional balanced sampling plans avoiding adjacent units, Discrete Mathematics, 338 (2015), 1624-1642.  doi: 10.1016/j.disc.2015.04.012.  Google Scholar

[28]

J. H. Wright, Two-dimensional balanced sampling plans excluding adjacent units, Journal of Statistical Planning and Inference, 138 (2008), 145-153.  doi: 10.1016/j.jspi.2007.05.016.  Google Scholar

[29]

J. H. Wright and J. Stufken, New balanced sampling plans excluding adjacent units, Journal of Statistical Planning and Inference, 138 (2008), 3326-3335.  doi: 10.1016/j.jspi.2006.10.020.  Google Scholar

[30]

J. Zhang and Y. X. Chang, The spectrum of cyclic BSEC with block size three, Discrete Mathematics, 305 (2005), 312-322.  doi: 10.1016/j.disc.2005.06.030.  Google Scholar

[31]

J. Zhang and Y. X. Chang, The spectrum of cyclic BSA $(v, 3, \lambda; \alpha)$ with $\alpha=2, 3$, Journal of Combinatorial Designs, 13 (2005), 313-335.  doi: 10.1002/jcd.20049.  Google Scholar

[32]

J. Zhang and Y. X. Chang, The spectrum of {BSA ($v$, 3, $\lambda$; $\alpha$)} with $\alpha$= 2, 3, Journal of Combinatorial Designs, 15 (2007), 61-76.  doi: 10.1002/jcd.20104.  Google Scholar

[33]

J. Zhang and Y. X. Chang, Existence of BSAs and cyclic BSAs of block size three, Journal of Statistical Planning and Inference, 137 (2007), 1496-1511.  doi: 10.1016/j.jspi.2006.02.009.  Google Scholar

[34]

J. Zhang and Y. X. Chang, Partitionable sets and cyclic BSECs with block size four, Journal of Statistical Planning and Inference, 139 (2009), 1974-1979.  doi: 10.1016/j.jspi.2008.09.007.  Google Scholar

show all references

References:
[1]

D. Bertozzi, L. Benini and G. D. Micheli, Low power error resilient encoding for on-chip data buses, Proceedings of the Conference on Design, Automation and Test in Europe, IEEE Computer Society, (2002), 102–109. doi: 10.1109/DATE.2002.998256.  Google Scholar

[2]

J. A. Bondy and U. S. R. Murty, Graph Theory with Applications, American Elsevier Publishing Co., Inc., New York, 1976.  Google Scholar

[3]

D. Bryant, Y. X. Chang, C. A. Rodger and R. Wei, Two-dimensional balanced sampling plans excluding contiguous units, Communications in Statistics-Theory and Methods, 31 (2002), 1441-1455.  doi: 10.1081/STA-120006078.  Google Scholar

[4]

Y. M. Chee, C. J. Colbourn and A. C. H. Ling, Optimal memoryless encoding for low power off-chip data buses, 2006 IEEE/ACM International Conference on Computer Aided Design, IEEE, (2006), 369–374. doi: 10.1145/1233501.1233575.  Google Scholar

[5]

Y. M. Chee, C. J. Colbourn, A. C. H. Ling, H. Zhang and X. D. Zhang, Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses, Des. Codes Cryptogr., 77 (2015), 479-491.  doi: 10.1007/s10623-015-0084-4.  Google Scholar

[6]

C. J. Colbourn and A. C. H. Ling, A class of partial triple systems with applications in survey sampling, Communications in Statistics-Theory and Methods, 27 (1998), 1009-1018.  doi: 10.1080/03610929808832141.  Google Scholar

[7]

C. J. Colbourn and A. C. H. Ling, Balanced sampling plans with block size four excluding contiguous units, Australasian Journal of Combinatorics, 20 (1999), 37-46. doi: ajc.maths.uq.edu.au.  Google Scholar

[8]

C. J. Duan, A. Tirumala and S. P. Khatri, Analysis and avoidance of cross-talk in on-chip buses, HOT 9 Interconnects Symposium on High Performance Interconnects, IEEE, (2001), 133–138. doi: 10.1109/HIS.2001.946705.  Google Scholar

[9]

M. Favalli and C. Metra, Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7 (1999), 392-396.  doi: 10.1109/92.784100.  Google Scholar

[10]

A. S. Hedayat, C. R. Rao and J. Stufken, Sampling plans excluding contiguous units, Sampling, Handbook of Statist., North-Holland, Amsterdam, 6 (1988), 575-583.  doi: 10.1016/0378-3758(88)90070-5.  Google Scholar

[11]

A. Hedayat, C. Rao and J. Stufken, 24 Designs in survey sampling avoiding contiguous units, Handbook of Statistics, 6 (1988), 575-583.  doi: 10.1016/S0169-7161(88)06026-2.  Google Scholar

[12]

I. Iqbal, M. H. Tahir, M. Akhtar, S. S. A. Ghazali, J. Shabbir and N. S. Bukhari, Generalized polygonal designs with block size 3 and $\lambda = 1$, Journal of Statistical Planning and Inference, 139 (2009), 3200-3219.  doi: 10.1016/j.jspi.2009.02.018.  Google Scholar

[13]

Z. Khan, T. Arslan and A. T. Erdogan, A dual low power and crosstalk immune encoding scheme for system-on-chip buses, International Workshop on Power and Timing Modeling, Optimization and Simulation, (2004), 585–592. doi: 10.1007/978-3-540-30205-6_60.  Google Scholar

[14]

H. R. Kong, J. G. Lei and Y. Zhang, On constructions for two dimensional balanced sampling plan excluding contiguous units with block size four, Discrete Mathematics, 308 (2008), 3729-3743.  doi: 10.1016/j.disc.2007.07.065.  Google Scholar

[15]

F. J. MacWilliams and N. J. A. Sloane, The Theory of Error-Correcting Codes. I, North-Holland Mathematical Library, Vol. 16. North-Holland Publishing Co., Amsterdam-New York-Oxford, 1977.  Google Scholar

[16]

Y. Miao and L. Zhu, Existence of incomplete group divisible designs, J. Comb. Math. Comb. Comput., 6 (1989), 33-49.   Google Scholar

[17]

K. N. Patel and I. L. Markov, Error-correction and crosstalk avoidance in DSM busses, Proceedings of the 2003 International Workshop on System-level Interconnect Prediction, ACM, (2003), 9–14. doi: 10.1145/639929.639933.  Google Scholar

[18]

S. Ramprasad, N. R. Shanbhag and I. N. Hajj, A coding framework for low-power address and data busses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7 (1999), 212-221.  doi: 10.1109/92.766748.  Google Scholar

[19]

D. Rossi, V. E. S. van Dijk, R. P. Kleihorst, A. H. Nieuwland and C. Metra, Coding scheme for low energy consumption fault-tolerant bus, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW), IEEE, (2002), 8–12. doi: 10.1109/OLT.2002.1030176.  Google Scholar

[20]

J. E. Simpson, Langford sequences: Perfect and hooked, Discrete Mathematics, 44 (1983), 97-104.  doi: 10.1016/0012-365X(83)90008-0.  Google Scholar

[21]

M. R. Stan and W. P. Burleson, Bus-invert coding for low-power I/O, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3 (1995), 49-58.  doi: 10.1109/92.365453.  Google Scholar

[22]

J. Stufken, Combinatorial and statistical aspects of sampling plans to avoid the selection of adjacent units, J. Combin. Info. Syst. Sci., 18 (1993), 149-160.   Google Scholar

[23]

J. Stufken and J. H. Wright, Polygonal designs with blocks of size $k \leq 10$, Metrika, 54 (2001), 179-184.  doi: 10.1007/s001840100137.  Google Scholar

[24]

C.-L. Su, C.-Y. Tsui and A. M. Despain, Saving power in the control path of embedded processors, IEEE Design Test of Computers, 11 (1994), 24-31.  doi: 10.1109/54.329448.  Google Scholar

[25]

M. H. Tahir, I. Iqbal, M. Akhtar and J. Shabbir, Cyclic polygonal designs with block size 3 and $\lambda = 1$ for joint distance $\alpha = 6$ to $16$, Journal of Statistical Theory and Practice, 4 (2010), 203-220.  doi: 10.1080/15598608.2010.10411981.  Google Scholar

[26]

B. Victor and K. Keutzer, Bus encoding to prevent crosstalk delay, Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, (2001), 57–63. doi: 10.1109/ICCAD.2001.968598.  Google Scholar

[27]

X. M. Wang, T. Feng, J. Zhang and Y. Xu, Two-dimensional balanced sampling plans avoiding adjacent units, Discrete Mathematics, 338 (2015), 1624-1642.  doi: 10.1016/j.disc.2015.04.012.  Google Scholar

[28]

J. H. Wright, Two-dimensional balanced sampling plans excluding adjacent units, Journal of Statistical Planning and Inference, 138 (2008), 145-153.  doi: 10.1016/j.jspi.2007.05.016.  Google Scholar

[29]

J. H. Wright and J. Stufken, New balanced sampling plans excluding adjacent units, Journal of Statistical Planning and Inference, 138 (2008), 3326-3335.  doi: 10.1016/j.jspi.2006.10.020.  Google Scholar

[30]

J. Zhang and Y. X. Chang, The spectrum of cyclic BSEC with block size three, Discrete Mathematics, 305 (2005), 312-322.  doi: 10.1016/j.disc.2005.06.030.  Google Scholar

[31]

J. Zhang and Y. X. Chang, The spectrum of cyclic BSA $(v, 3, \lambda; \alpha)$ with $\alpha=2, 3$, Journal of Combinatorial Designs, 13 (2005), 313-335.  doi: 10.1002/jcd.20049.  Google Scholar

[32]

J. Zhang and Y. X. Chang, The spectrum of {BSA ($v$, 3, $\lambda$; $\alpha$)} with $\alpha$= 2, 3, Journal of Combinatorial Designs, 15 (2007), 61-76.  doi: 10.1002/jcd.20104.  Google Scholar

[33]

J. Zhang and Y. X. Chang, Existence of BSAs and cyclic BSAs of block size three, Journal of Statistical Planning and Inference, 137 (2007), 1496-1511.  doi: 10.1016/j.jspi.2006.02.009.  Google Scholar

[34]

J. Zhang and Y. X. Chang, Partitionable sets and cyclic BSECs with block size four, Journal of Statistical Planning and Inference, 139 (2009), 1974-1979.  doi: 10.1016/j.jspi.2008.09.007.  Google Scholar

Figure 1.  Leave graphs of LPSA$ (6n,3;2) $ having $ 3n $ edges
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Figure 2.  Points of the hole are denoted by $ \bullet $ and others by $ \circ $
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Figure 3.  Points of the hole are denoted by $ \bullet $ and others by $ \circ $
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Table 1.  Types of worst crosstalk couplings
Type-Ⅰ Type-Ⅱ Type-Ⅲ Type-Ⅳ
$ 0\longleftrightarrow1 $ $ 001\longleftrightarrow010 $ $ 010\longleftrightarrow101 $
$ 001\longleftrightarrow110 $ $ 010\longleftrightarrow100 $
$ 011\longleftrightarrow100 $ $ 011\longleftrightarrow101 $
$ 101\longleftrightarrow110 $
Single wire undergoes transition. Adjacent wires maintain previous states Center wire in opposite transition to an adjacent wire. The other wire in same transition as center wire Center wire in opposite transition to an adjacent wire. The other wire maintains previous state All three adjacent wires undergo opposite transitions
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Type-Ⅰ Type-Ⅱ Type-Ⅲ Type-Ⅳ
$ 0\longleftrightarrow1 $ $ 001\longleftrightarrow010 $ $ 010\longleftrightarrow101 $
$ 001\longleftrightarrow110 $ $ 010\longleftrightarrow100 $
$ 011\longleftrightarrow100 $ $ 011\longleftrightarrow101 $
$ 101\longleftrightarrow110 $
Single wire undergoes transition. Adjacent wires maintain previous states Center wire in opposite transition to an adjacent wire. The other wire in same transition as center wire Center wire in opposite transition to an adjacent wire. The other wire maintains previous state All three adjacent wires undergo opposite transitions
Table 2.  Upper bounds and leave graphs of CPSAs and LPSAs excluding edges within distance two
Sampling plans Upper bounds Leave graphs
CPSA$ (6n,3;2) $ $ 6n(n-1) $ A perfect matching
CPSA$ (6n+1,3;2) $ $ n(6n-3)-2 $ A cycle of length four
LPSA$ (6n,3;2) $ $ 6n(n-1)+1 $ see Fig. 1
LPSA$ (6n+1,3;2) $ $ n(6n-3) $ A single edge
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Sampling plans Upper bounds Leave graphs
CPSA$ (6n,3;2) $ $ 6n(n-1) $ A perfect matching
CPSA$ (6n+1,3;2) $ $ n(6n-3)-2 $ A cycle of length four
LPSA$ (6n,3;2) $ $ 6n(n-1)+1 $ see Fig. 1
LPSA$ (6n+1,3;2) $ $ n(6n-3) $ A single edge
Table 3.  Existence results of small orders
$ n $ $ 24 $ $ 25 $ $ 30 $ $ 31 $ $ 36 $ $ 37 $ $ 48 $ $ 49 $
$ B^{\circ}(n,3;2) $ $ - $ $ 82 $ $ - $ $ 133 $ $ - $ $ 196 $ $ 336 $ $ 358 $
$ B(n,3;2) $ $ 73 $ $ 84 $ $ 121 $ $ 135 $ $ 181 $ $ 198 $ $ 337 $ $ 360 $
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$ n $ $ 24 $ $ 25 $ $ 30 $ $ 31 $ $ 36 $ $ 37 $ $ 48 $ $ 49 $
$ B^{\circ}(n,3;2) $ $ - $ $ 82 $ $ - $ $ 133 $ $ - $ $ 196 $ $ 336 $ $ 358 $
$ B(n,3;2) $ $ 73 $ $ 84 $ $ 121 $ $ 135 $ $ 181 $ $ 198 $ $ 337 $ $ 360 $
Table 4.  Parameters for proof of Lemma 4.6
n=3g+t-1 g t s
72s=3(24(s-1)+18)+18 24(s-1)+18 19 $s\geq 1, \ s\neq 1$
72s+24=3(24(s-1)+18)+42 24(s-1)+18 43 $s\geq 1, \ s\neq 1,2,3$
72s+48=3(24s+12)+12 24s+12 13 $s\geq 1$
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n=3g+t-1 g t s
72s=3(24(s-1)+18)+18 24(s-1)+18 19 $s\geq 1, \ s\neq 1$
72s+24=3(24(s-1)+18)+42 24(s-1)+18 43 $s\geq 1, \ s\neq 1,2,3$
72s+48=3(24s+12)+12 24s+12 13 $s\geq 1$
Table 5.  Parameters for proof of Lemma 4.8
$n\quad \ \ \ \ \ \ =3g+t$ $g$ $t$ $s$
$72s+1 \ =3(24(s-1)+18)+19$ $24(s-1)+18$ $19$ $s\geq 1,\ s\neq 1$
$72s+7 \ =3(24s)+7$ $24s$ $7$ $s\geq 1$
$72s+13=3(24(s-1)+18)+31$ $24(s-1)+18$ $31$ $s\geq 1,\ s\neq 1,2,3$
$72s+19=3(24s+6)+1$ $24s+6$ $1$ $s\geq 1$
$72s+25=3(24(s-1)+18)+43$ $24(s-1)+18$ $43$ $s\geq 1, \ s\neq 1,2,3$
$72s+31=3(24s+6)+13$ $24s+6$ $13$ $s\geq 1, \ s\neq 1$
$72s+37=3(24(s-1)+12)+1$ $24(s-1)+12$ $1$ $s\geq 1, \ s\neq 1$
$72s+43=3(24s+6)+25$ $24s+6$ $25$ $s\geq 1, \ s\neq 1$
$72s+49=3(24s+12)+13$ $24s+12$ $13$ $s\geq 1$
$72s+55=3(24s+18)+1$ $24s+18$ $1$ $s\geq 1$
$72s+61=3(24s+18)+7$ $24s+18$ $7$ $s\geq 1$
$72s+67=3(24s+6)+49$ $24s+6$ $49$ $s\geq 1, \ s\neq 1,2,3$
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$n\quad \ \ \ \ \ \ =3g+t$ $g$ $t$ $s$
$72s+1 \ =3(24(s-1)+18)+19$ $24(s-1)+18$ $19$ $s\geq 1,\ s\neq 1$
$72s+7 \ =3(24s)+7$ $24s$ $7$ $s\geq 1$
$72s+13=3(24(s-1)+18)+31$ $24(s-1)+18$ $31$ $s\geq 1,\ s\neq 1,2,3$
$72s+19=3(24s+6)+1$ $24s+6$ $1$ $s\geq 1$
$72s+25=3(24(s-1)+18)+43$ $24(s-1)+18$ $43$ $s\geq 1, \ s\neq 1,2,3$
$72s+31=3(24s+6)+13$ $24s+6$ $13$ $s\geq 1, \ s\neq 1$
$72s+37=3(24(s-1)+12)+1$ $24(s-1)+12$ $1$ $s\geq 1, \ s\neq 1$
$72s+43=3(24s+6)+25$ $24s+6$ $25$ $s\geq 1, \ s\neq 1$
$72s+49=3(24s+12)+13$ $24s+12$ $13$ $s\geq 1$
$72s+55=3(24s+18)+1$ $24s+18$ $1$ $s\geq 1$
$72s+61=3(24s+18)+7$ $24s+18$ $7$ $s\geq 1$
$72s+67=3(24s+6)+49$ $24s+6$ $49$ $s\geq 1, \ s\neq 1,2,3$
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