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Efficient systolic multiplications in composite fields for cryptographic systems
School of Computer Engineering Shenzhen Polytechnic, Shenzhen 518055, China |
Multiplications in finite fields are playing a key role in areas of cryptography and mathematic. We present approaches to exploit systolic architecture for multiplications in composite fields, which are expected to reduce the time-area product substantially. We design a pipelined architecture for multiplications in composite fields $GF({({2^n})^2})$, where $n$ is a positive integer. Besides, we design systolic architectures for multiplications and additions in finite fields $GF(2^n)$. By integrating main improvements and other minor optimizations for multiplications in $GF({({2^n})^2})$, the non-pipelined versions of our design takes $8n+4$ AND gates and $8n$ XOR gates to compute multiplications with the executing time of $nT_{AND}+4nT_{XOR}$, where $T_{AND}$ and ${T_{XOR}}$ are delays of AND and XOR gates respectively; with the aid of pipelining, the pipelined version of our design has a throughput rate of one result per $2nT_{XOR}$. Other words, the time complexity and area complexity of our design are $O(n)$. Thus, the complexity of time-area product of our design is $O(n^2)$. Experimental results and comparisons show that our design provides significant reductions in executing time and area of multiplications.
References:
[1] |
N. Ahmad and S. M. R. Hasan,
Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate, Integration the VLSI Journal, 46 (2013), 333-344.
|
[2] |
R. Azarderakhsh,
Mozaffari-kermani M. high-performance two-dimensional finite field multiplication and exponentiation for cryptographic applications, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34 (2015), 1569-1576.
|
[3] |
S. Ballet and R. Rolland,
Multiplication algorithm in a finite field and tensor rank of the multiplication, Journal of Algebra, 272 (2004), 173-185.
doi: 10.1016/j.jalgebra.2003.09.031. |
[4] |
C. Berrou and A. Glavieux,
Near optimum error correcting coding and decoding: Turbo-codes, IEEE Transactions on Communications, 44 (1996), 1261-1271.
|
[5] |
D. Canright, A very compact S-box for AES, Cryptographic Hardware and Embedded Systems - CHES 2005, International Workshop, Edinburgh, Uk, August 29 - September 1, 2005, Proceedings. DBLP, 2005, 441-455. |
[6] |
M. Cenk, C. K. Koc and F. Ozbudak, Polynomial multiplication over finite fields using field extensions and interpolation, IEEE Symposium on Computer Arithmetic, IEEE Computer Society, 2009, 84-91. |
[7] |
A. Cichocki and R. Unbehauen,
Neural networks for solving systems of linear equations and related problems, IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications, 39 (1992), 124-138.
|
[8] |
M. Diab, Systolic architectures for multiplication over finite field $ GF(2^m)$, International Symposium on Applied Algebra, Algebraic Algorithms and Error-Correcting Codes, Springer-Verlag, 1991, 329-340.
doi: 10.1007/3-540-54195-0_62. |
[9] |
A. Hariri,
Concurrent error detection in montgomery multiplication over binary extension fields, IEEE Transactions on Computers, 60 (2011), 1341-1353.
doi: 10.1109/TC.2010.258. |
[10] |
M. A. Hasan, Look-up table based large finite field multiplication in memory constrained cryptosystems, Cryptography and Coding, IMA International Conference, Cirencester, Uk, December 20-22, 1999, Proceedings. DBLP, 1746 (1999), 213-221.
doi: 10.1007/3-540-46665-7_25. |
[11] |
Z. Huang, G. Q. Bai and H. Y. Chen,
FPGA Implementation of Systolic Array for Modular Multiplication Using a Fine-grained Approach, Microelectronics and Computer, 2005. |
[12] |
S. K. Jain, L. Song and K. K. Parhi,
Efficient semisystolic architectures for finite-field arithmetic, IEEE Transactions on Very Large Scale Integration Systems, 6 (1998), 101-113.
|
[13] |
R. Katti and J. Brennan,
Low complexity multiplication in a finite field using ring representation, IEEE Transactions on Computers, 52 (2003), 418-427.
|
[14] |
C. H. Kim, C. P. Hong and S. Kwon,
A digit-serial multiplier for finite field $ GF(2^m)$, IEEE Transactions on Very Large Scale Integration Systems, 13 (2005), 476-483.
|
[15] |
C. Y. Lee and W. C. Che,
New bit-parallel systolic architectures for computing multiplication, multiplicative inversion and division in $ gf(2^m)$ under polynomial basis and normal basis representations, Journal of Signal Processing Systems, 52 (2008), 313-324.
|
[16] |
D. J. C. Mackay,
Good error-correcting codes based on very sparse matrices, IEEE Transactions on Information Theory, 45 (1999), 399-431.
doi: 10.1109/18.748992. |
[17] |
P. K. Meher, Systolic formulation for low-complexity serial-parallel implementation of unified finite field multiplication over $ GF(2^m)$, IEEE International Conf. on Application -specific Systems, Architectures and Processors. 2007, 134-139. |
[18] |
P. K. Meher,
Systolic and super-systolic multipliers for finite field $ GF(2^m)$ based on irreducible trinomials, IEEE Transactions on Circuits and Systems, 55 (2008), 1031-1040.
doi: 10.1109/TCSI.2008.916622. |
[19] |
A. H. Namin, H. Wu and M. Ahmadi,
Comb architectures for finite field multiplication in $ F(2^m)$, IEEE Transactions on Computers, 56 (2007), 909-916.
doi: 10.1109/TC.2007.1047. |
[20] |
S. H. Namin, H. Wu and M. Ahmadi,
Low-power design for a digit-serial polynomial basis finite field multiplier using factoring technique, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25 (2017), 441-449.
|
[21] |
P. Ning and Y. L. Yin, Efficient software implementation for finite field multiplication in normal basis, International Conference on Information and Communications Security, Springer-Verlag, 2001,177-188. |
[22] |
J. S. Pan, C. Y. Lee and P. K. Meher,
Low-latency digit-serial and digit-parallel systolic multipliers for large binary extension fields, IEEE Transactions on Circuits & Systems I Regular Papers, 60 (2013), 3195-3204.
|
[23] |
A. Petzoldt, S. Bulygin and J. Buchmann, Selecting parameters for the rainbow signature scheme, Post-Quantum Cryptography, Third International Workshop, PQCrypto 2010, Darmstadt, Germany, May 25-28, 2010. Proceedings. DBLP, 2010,218-240.
doi: 10.1007/978-3-642-12929-2_16. |
[24] |
A. Pincin,
A new algorithm for multiplication in finite fields, IEEE Transactions on Computers, 38 (1989), 1045-1049.
doi: 10.1109/12.30855. |
[25] |
A. Reyhani-Masoleh and M. A. Hasan,
Low complexity bit parallel architectures for polynomial basis multiplication over $ GF(2^m)$, IEEE Transactions on Computers, 53 (2004), 945-959.
|
[26] |
A. Satoh, S. Morioka and K. Takano, et al., A compact rijndael hardware architecture with S-box optimization, Advances in Cryptology-ASIACRYPT 2001., Springer Berlin Heidelberg, 2248 (2001), 239-254.
doi: 10.1007/3-540-45682-1_15. |
[27] |
T. Shirai, K. Shibutani and T. Akishita, et al., The 128-bit blockcipher CLEFIA, Proceedings of the 14th International Conference on Fast Software Encryption, Springer-Verlag, 2007,181-195. |
[28] |
M. Sudan,
Decoding of reed solomon codes beyond the error-correction bound, Journal of Complexity, 13 (1997), 180-193.
doi: 10.1006/jcom.1997.0439. |
[29] |
S. Tang, H. Yi and J. Ding, et al., High-speed hardware implementation of rainbow signature on FPGAs, Post-Quantum Cryptography. Springer Berlin Heidelberg, 2011,228-243. |
[30] |
C. L. Wang and J. L. Lin,
Systolic array implementation of multipliers for finite fields $ GF(2^m)$, IEEE Transactions on Circuits and Systems, 38 (1991), 796-800.
|
[31] |
C. W. Wu and M. K. Chang,
Bit-level systolic arrays for finite-field multiplications, Journal of Signal Processing Systems, 10 (1995), 85-92.
|
[32] |
H. Wu,
Bit-parallel finite field multiplier and squarer using polynomial basis, IEEE Transactions on Computers, 51 (2002), 750-758.
doi: 10.1109/TC.2002.1017695. |
[33] |
J. Xie, J. J. He and P. K. Meher,
Low latency systolic montgomery multiplier for finite field $ GF(2^m)$ based on pentanomials, IEEE Transactions on Very Large Scale Integration Systems, 21 (2013), 385-389.
|
[34] |
J. Xie, P. K. Meher and Z. H. Mao,
Low-latency high-throughput systolic multipliers over $ GF(2^m)$ for NIST recommended pentanomials, IEEE Transactions on Circuits & Systems I Regular Papers, 62 (2015), 881-890.
doi: 10.1109/TCSI.2014.2386782. |
[35] |
H. Yi and W. Li,
Fast three-input multipliers over small composite fields for multivariate public key cryptography, International Journal of Security and Its Applications, 9 (2015), 165-178.
|
[36] |
H. Yi, W. Li and Z. Nie,
Fast hardware implementations of inversions in small finite fields for special irreducible polynomials on FPGAs, International Journal of Security and Its Applications, 19 (2016), 109-C120.
|
[37] |
H. Yi and S. Tang,
Very small FPGA processor for multivariate signatures, Computer Journal, 59 (2016), 1091-1101.
doi: 10.1093/comjnl/bxw008. |
[38] |
H. Yi, S. Tang and R. Vemuri,
Fast inversions in small finite fields by using binary trees, The Computer Journal, 59 (2016), 1102-1112.
doi: 10.1093/comjnl/bxw009. |
show all references
References:
[1] |
N. Ahmad and S. M. R. Hasan,
Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate, Integration the VLSI Journal, 46 (2013), 333-344.
|
[2] |
R. Azarderakhsh,
Mozaffari-kermani M. high-performance two-dimensional finite field multiplication and exponentiation for cryptographic applications, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34 (2015), 1569-1576.
|
[3] |
S. Ballet and R. Rolland,
Multiplication algorithm in a finite field and tensor rank of the multiplication, Journal of Algebra, 272 (2004), 173-185.
doi: 10.1016/j.jalgebra.2003.09.031. |
[4] |
C. Berrou and A. Glavieux,
Near optimum error correcting coding and decoding: Turbo-codes, IEEE Transactions on Communications, 44 (1996), 1261-1271.
|
[5] |
D. Canright, A very compact S-box for AES, Cryptographic Hardware and Embedded Systems - CHES 2005, International Workshop, Edinburgh, Uk, August 29 - September 1, 2005, Proceedings. DBLP, 2005, 441-455. |
[6] |
M. Cenk, C. K. Koc and F. Ozbudak, Polynomial multiplication over finite fields using field extensions and interpolation, IEEE Symposium on Computer Arithmetic, IEEE Computer Society, 2009, 84-91. |
[7] |
A. Cichocki and R. Unbehauen,
Neural networks for solving systems of linear equations and related problems, IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications, 39 (1992), 124-138.
|
[8] |
M. Diab, Systolic architectures for multiplication over finite field $ GF(2^m)$, International Symposium on Applied Algebra, Algebraic Algorithms and Error-Correcting Codes, Springer-Verlag, 1991, 329-340.
doi: 10.1007/3-540-54195-0_62. |
[9] |
A. Hariri,
Concurrent error detection in montgomery multiplication over binary extension fields, IEEE Transactions on Computers, 60 (2011), 1341-1353.
doi: 10.1109/TC.2010.258. |
[10] |
M. A. Hasan, Look-up table based large finite field multiplication in memory constrained cryptosystems, Cryptography and Coding, IMA International Conference, Cirencester, Uk, December 20-22, 1999, Proceedings. DBLP, 1746 (1999), 213-221.
doi: 10.1007/3-540-46665-7_25. |
[11] |
Z. Huang, G. Q. Bai and H. Y. Chen,
FPGA Implementation of Systolic Array for Modular Multiplication Using a Fine-grained Approach, Microelectronics and Computer, 2005. |
[12] |
S. K. Jain, L. Song and K. K. Parhi,
Efficient semisystolic architectures for finite-field arithmetic, IEEE Transactions on Very Large Scale Integration Systems, 6 (1998), 101-113.
|
[13] |
R. Katti and J. Brennan,
Low complexity multiplication in a finite field using ring representation, IEEE Transactions on Computers, 52 (2003), 418-427.
|
[14] |
C. H. Kim, C. P. Hong and S. Kwon,
A digit-serial multiplier for finite field $ GF(2^m)$, IEEE Transactions on Very Large Scale Integration Systems, 13 (2005), 476-483.
|
[15] |
C. Y. Lee and W. C. Che,
New bit-parallel systolic architectures for computing multiplication, multiplicative inversion and division in $ gf(2^m)$ under polynomial basis and normal basis representations, Journal of Signal Processing Systems, 52 (2008), 313-324.
|
[16] |
D. J. C. Mackay,
Good error-correcting codes based on very sparse matrices, IEEE Transactions on Information Theory, 45 (1999), 399-431.
doi: 10.1109/18.748992. |
[17] |
P. K. Meher, Systolic formulation for low-complexity serial-parallel implementation of unified finite field multiplication over $ GF(2^m)$, IEEE International Conf. on Application -specific Systems, Architectures and Processors. 2007, 134-139. |
[18] |
P. K. Meher,
Systolic and super-systolic multipliers for finite field $ GF(2^m)$ based on irreducible trinomials, IEEE Transactions on Circuits and Systems, 55 (2008), 1031-1040.
doi: 10.1109/TCSI.2008.916622. |
[19] |
A. H. Namin, H. Wu and M. Ahmadi,
Comb architectures for finite field multiplication in $ F(2^m)$, IEEE Transactions on Computers, 56 (2007), 909-916.
doi: 10.1109/TC.2007.1047. |
[20] |
S. H. Namin, H. Wu and M. Ahmadi,
Low-power design for a digit-serial polynomial basis finite field multiplier using factoring technique, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25 (2017), 441-449.
|
[21] |
P. Ning and Y. L. Yin, Efficient software implementation for finite field multiplication in normal basis, International Conference on Information and Communications Security, Springer-Verlag, 2001,177-188. |
[22] |
J. S. Pan, C. Y. Lee and P. K. Meher,
Low-latency digit-serial and digit-parallel systolic multipliers for large binary extension fields, IEEE Transactions on Circuits & Systems I Regular Papers, 60 (2013), 3195-3204.
|
[23] |
A. Petzoldt, S. Bulygin and J. Buchmann, Selecting parameters for the rainbow signature scheme, Post-Quantum Cryptography, Third International Workshop, PQCrypto 2010, Darmstadt, Germany, May 25-28, 2010. Proceedings. DBLP, 2010,218-240.
doi: 10.1007/978-3-642-12929-2_16. |
[24] |
A. Pincin,
A new algorithm for multiplication in finite fields, IEEE Transactions on Computers, 38 (1989), 1045-1049.
doi: 10.1109/12.30855. |
[25] |
A. Reyhani-Masoleh and M. A. Hasan,
Low complexity bit parallel architectures for polynomial basis multiplication over $ GF(2^m)$, IEEE Transactions on Computers, 53 (2004), 945-959.
|
[26] |
A. Satoh, S. Morioka and K. Takano, et al., A compact rijndael hardware architecture with S-box optimization, Advances in Cryptology-ASIACRYPT 2001., Springer Berlin Heidelberg, 2248 (2001), 239-254.
doi: 10.1007/3-540-45682-1_15. |
[27] |
T. Shirai, K. Shibutani and T. Akishita, et al., The 128-bit blockcipher CLEFIA, Proceedings of the 14th International Conference on Fast Software Encryption, Springer-Verlag, 2007,181-195. |
[28] |
M. Sudan,
Decoding of reed solomon codes beyond the error-correction bound, Journal of Complexity, 13 (1997), 180-193.
doi: 10.1006/jcom.1997.0439. |
[29] |
S. Tang, H. Yi and J. Ding, et al., High-speed hardware implementation of rainbow signature on FPGAs, Post-Quantum Cryptography. Springer Berlin Heidelberg, 2011,228-243. |
[30] |
C. L. Wang and J. L. Lin,
Systolic array implementation of multipliers for finite fields $ GF(2^m)$, IEEE Transactions on Circuits and Systems, 38 (1991), 796-800.
|
[31] |
C. W. Wu and M. K. Chang,
Bit-level systolic arrays for finite-field multiplications, Journal of Signal Processing Systems, 10 (1995), 85-92.
|
[32] |
H. Wu,
Bit-parallel finite field multiplier and squarer using polynomial basis, IEEE Transactions on Computers, 51 (2002), 750-758.
doi: 10.1109/TC.2002.1017695. |
[33] |
J. Xie, J. J. He and P. K. Meher,
Low latency systolic montgomery multiplier for finite field $ GF(2^m)$ based on pentanomials, IEEE Transactions on Very Large Scale Integration Systems, 21 (2013), 385-389.
|
[34] |
J. Xie, P. K. Meher and Z. H. Mao,
Low-latency high-throughput systolic multipliers over $ GF(2^m)$ for NIST recommended pentanomials, IEEE Transactions on Circuits & Systems I Regular Papers, 62 (2015), 881-890.
doi: 10.1109/TCSI.2014.2386782. |
[35] |
H. Yi and W. Li,
Fast three-input multipliers over small composite fields for multivariate public key cryptography, International Journal of Security and Its Applications, 9 (2015), 165-178.
|
[36] |
H. Yi, W. Li and Z. Nie,
Fast hardware implementations of inversions in small finite fields for special irreducible polynomials on FPGAs, International Journal of Security and Its Applications, 19 (2016), 109-C120.
|
[37] |
H. Yi and S. Tang,
Very small FPGA processor for multivariate signatures, Computer Journal, 59 (2016), 1091-1101.
doi: 10.1093/comjnl/bxw008. |
[38] |
H. Yi, S. Tang and R. Vemuri,
Fast inversions in small finite fields by using binary trees, The Computer Journal, 59 (2016), 1102-1112.
doi: 10.1093/comjnl/bxw009. |


Stage | Clock Cycle | Executing Time | Area (Logic Gates) |
0 | |||
1 | |||
2 | |||
Total |
Stage | Clock Cycle | Executing Time | Area (Logic Gates) |
0 | |||
1 | |||
2 | |||
Total |
Input | Starting Time | Ending Time |
0 | ||
|
||
|
||
|
||
Input | Starting Time | Ending Time |
0 | ||
|
||
|
||
|
||
Field | Clock Cycle | Executing Time | Throughput | Cells | Area (Logic Gates) |
Field | Clock Cycle | Executing Time | Throughput | Cells | Area (Logic Gates) |
Finite Field | |||||||||||
1.4 | 0.6 | 478.8 | 16.8 | 7.1 | 48 | 17.8 | 7.2 | 45 | |||
|
2.8 | 1.2 | 904.4 | 34.4 | 14.1 | 89 | 35.9 | 14.2 | 83 | ||
|
9.1 | 3.7 | 2819.6 | 116.4 | 44.6 | 245 | < 1% | 117.3 | 46.3 | 232 | < 1% |
|
11.9 | 4.8 | 3670.8 | 147.7 | 58.4 | 313 | < 1% | 152.6 | 60.8 | 298 | < 1% |
|
21.7 | 8.8 | 6650.2 | 271.1 | 102.4 | 557 | < 1% | 275.9 | 110.4 | 537 | < 1% |
|
25.9 | 10.3 | 7926.8 | 321.9 | 125.9 | 634 | < 1% | 329.3 | 131.7 | 614 | < 1% |
|
42.7 | 17.1 | 13034.2 | 541.4 | 211.8 | 1023 | < 1% | 542.9 | 217.2 | 998 | 1.44% |
|
46.7 | 18.8 | 14310.8 | 574.2 | 233.1 | 1124 | < 1% | 589.6 | 238.5 | 1097 | 1.58% |
|
83.3 | 33.4 | 25376.4 | 1055.9 | 411.9 | 2012 | 1.41% | 1059.3 | 423.6 | 1927 | 2.79% |
|
88.9 | 33.6 | 27078.8 | 1134.6 | 446.3 | 2119 | 1.47% | 1141.6 | 456.8 | 2078 | 3.01% |
Finite Field | |||||||||||
1.4 | 0.6 | 478.8 | 16.8 | 7.1 | 48 | 17.8 | 7.2 | 45 | |||
|
2.8 | 1.2 | 904.4 | 34.4 | 14.1 | 89 | 35.9 | 14.2 | 83 | ||
|
9.1 | 3.7 | 2819.6 | 116.4 | 44.6 | 245 | < 1% | 117.3 | 46.3 | 232 | < 1% |
|
11.9 | 4.8 | 3670.8 | 147.7 | 58.4 | 313 | < 1% | 152.6 | 60.8 | 298 | < 1% |
|
21.7 | 8.8 | 6650.2 | 271.1 | 102.4 | 557 | < 1% | 275.9 | 110.4 | 537 | < 1% |
|
25.9 | 10.3 | 7926.8 | 321.9 | 125.9 | 634 | < 1% | 329.3 | 131.7 | 614 | < 1% |
|
42.7 | 17.1 | 13034.2 | 541.4 | 211.8 | 1023 | < 1% | 542.9 | 217.2 | 998 | 1.44% |
|
46.7 | 18.8 | 14310.8 | 574.2 | 233.1 | 1124 | < 1% | 589.6 | 238.5 | 1097 | 1.58% |
|
83.3 | 33.4 | 25376.4 | 1055.9 | 411.9 | 2012 | 1.41% | 1059.3 | 423.6 | 1927 | 2.79% |
|
88.9 | 33.6 | 27078.8 | 1134.6 | 446.3 | 2119 | 1.47% | 1141.6 | 456.8 | 2078 | 3.01% |
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