A simple digital spiking neural network: Synchronization and spike-train approximation

Hiroaki Uchida; Yuya Oishi; Toshimichi Saito

doi:10.3934/dcdss.2020374

Article Contents

2021, Volume 14, Issue 4: 1479-1494. Doi: 10.3934/dcdss.2020374

This issue Previous Article Finite-time exponential synchronization of reaction-diffusion delayed complex-dynamical networks Next Article Optimal synchronization control of multiple euler-lagrange systems via event-triggered reinforcement learning

A simple digital spiking neural network: Synchronization and spike-train approximation

Department of Electrical and Electronic Engineering, Faculty of Science and Engineering, Hosei University, Koganei, Tokyo, 184-8584, Japan

^* Corresponding author: Toshimichi Saito
^* Corresponding author: Toshimichi Saito

Received: October 2019

Revised: March 2020

Early access: May 2020

Published: April 2021

This work is supported in part by JSPS KAKENHI 18K11480

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Abstract

This paper studies synchronization phenomena of spike-trains and approximation of target spike-trains in a simple network of digital spiking neurons. Repeating integrate-and-fire behavior between a periodic base signal and constant firing threshold, the neurons can generate various spike-trains. Connecting multiple neurons by cross-firing with delay, the network is constructed. The network can exhibit multi-phase synchronization of various spike-trains. Stability of the synchronization phenomena can be guaranteed theoretically. Applying a simple winner-take-all switching, the network can approximate target spike-trains automatically. In order to evaluate the approximation performance, we present two metrics: spike-position error and spike missing rate. Using the metrics, approximation capability of the network is investigated in typical target signals. Presenting an FPGA based hardware prototype, typical synchronization phenomenon and spike-train approximation are confirmed experimentally.

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Mathematics Subject Classification: Primary: 37B15; Secondary: 93C62, 92B20.

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Figure 1. DSNs and Dmaps for $ T_p = 18 $. (a) A PST with period $ 6T_p $ and corresponding PEO with period 6. $ \delta = (16,17,18,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15) $. (b) A direct stable PST with period $ 6T_p $ and corresponding PEO with period 6. $ \delta = (17,17,17,2,2,2,5,5,5,8,8,8,11,11,11,14,14,14) $

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Figure 2. Digital spiking neural network (DSNN) in a ladder form

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Figure 3. Cross-firing

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Figure 4. 6-phase synchronization of PSTs with period 6 in DSNN

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Figure 5. Stability of master-slave synchronization

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Figure 6. WTA switching for $ M = 6 $. (a) WTA switching. (b) Target spike-train $ y_t $ and approximated spike-train $ y_a $

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Figure 7. Dmap for each DSN in the DSNN for $ T_p = 36 $ and $ M = 12 $. $ \delta = (35,35,35,2,2,2,5,5,5,8,8,8,11,11,11,14, $ $ 14,14,17,17,17,20,20,20,23,23,23,26,26,26,29,29,29,32,32,32) $. The PEO with period 12 corresponds to the PST with period $ 12T_p $

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Figure 8. Target PST $ y_t $, approximated PST $ y_a $, and 12-phase synchronization of of PSTs $ y_1 \sim y_{12} $ with period $ 12 $. Verilog simulation of DSNN for $ M = 12 $

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Figure 9. Discrete exponential distribution for target PSTs

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Figure 10. Selection of activated DSNs from 6DSNs. (a) Selection of spike missing: the 1st, the 2nd, and the 3rd DSNs. (b) Selection of no spike missing: the 1st, the 3rd, and the 5th DSNs

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Figure 11. Circuit design of DSNN with the WTA

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Figure 12. Target spike-train, approximated spike-train and multi-phase synchronization in an FPGA board

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Table 1. Case 1 results

#DSN	AVG $ \varepsilon_p $	SD $ \varepsilon_p $	SMR
3	6.60	1.35	30.3
4	5.17	0.74	17, 5
5	4.19	0.43	10.1
6	3.56	0.31	5.10
7	3.02	0.30	0.82
8	2.63	0.24	0
9	2.43	0.19	0
10	2.25	0.18	0
11	2.11	0.14	0
12	2.02	0.10	0

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Table 2. Case 2 results

#DSN	AVG $\varepsilon_p$	SD $\varepsilon_p$	SMR
3	8.91	1.84	44.5
4	6.22	0.90	21.7
5	5.12	0.74	10.8
6	4.18	0.46	2.78
7	3.62	0.44	1.09
8	3.22	0.30	0.27
9	2.91	0.29	0
10	2.59	0.22	0
11	2.28	0.14	0
12	2.03	0.11	0

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